1 idt49fct3805/a 3.3v cmos buffer/clock driver commercial and industrial temperature range september 2004 2004 integrated device technology, inc. dsc-3102/5 c idt49fct3805/a commercial and industrial temperature range 3.3v cmos buffer/clock driver description: the fct3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal cmos technology. the device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. the device has a "heartbeat" monitor for diagnostics and pll driving. the mon output is identical to all other outputs and complies with the output specifications in this document. the fct3805 offers low capacitance inputs with hysteresis. the fct3805 is designed for high speed clock distribution where signal quality and skew are critical. the fct3805 also allows single point-to- point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple recievers with low skew and high signal quality. for more information on using the fct3805 with two different input frequencies on bank a and b, please see an-236. functional block diagram 5 oa 1 - oa 5 ob 1 - ob 5 oe a in a oe b in b mon 5 pin configuration oa 1 oa 3 oa 4 gnd q in a v cca oa 2 gnd a oa 5 oe a 1 2 3 4 5 6 7 8 9 ob 3 ob 4 mon in b v ccb ob 1 ob 2 gnd b ob 5 oe b 11 12 13 14 15 16 17 18 19 20 10 soic/ ssop/ qsop top view features: ? 0.5 micron cmos technology ? guaranteed low skew < 500ps (max.) ? very low duty cycle distortion < 1.0ns (max.) ? very low cmos power levels ? ttl compatible inputs and outputs ? inputs can be driven from 3.3v or 5v components ? two independent output banks with 3-state control ? 1:5 fanout per bank ? "heartbeat" monitor output ?v cc = 3.3v 0.3v ? available in ssop, soic, and qsop packages the idt logo is a registered trademark of integrated device technology, inc.
2 commercial and industrial temperature range idt49fct3805/a 3.3v cmos buffer/clock driver absolute maximum ratings (1) symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to +7 v v term (4) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. input terminals. 4. outputs and i/o terminals. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf note: 1. this parameter is measured at characterization but not tested. pin description pin names description oe a , oe b 3-state output enable inputs (active low) in a , in b clock inputs oan, obn clock outputs m o n monitor output function table (1) inputs outputs oe a , oe b in a , in b oan, obn mon llll lhhh hlzl hh zh note: 1. h = high l = low z = high-impedance
3 idt49fct3805/a 3.3v cmos buffer/clock driver commercial and industrial temperature range dc electrical characteristics over operating range following conditions apply unless otherwise specified commercial: t a = 0c to +70c, industrial: t a = -40c to +85c, v cc = 3.3v 0.3v symbol parameter test conditions (1) min. typ. max. unit v ih input high level (input pins) guaranteed logic high level 2 ? 5.5 v input high level (i/o pins) 2 ? v cc + 0.5 v il input low level (input and i/o pins) guaranteed logic low level ?0.5 ? 0.8 v i ih input high current (input pins) v cc = max. v i = 5.5v ? ? 1 input high current (i/o pins) v i = v cc ?? 1a i il input low current (input pins) v cc = max. v i = gnd ? ? 1 input low current (i/o pins) v i = gnd ? ? 1 i ozh high impedence output current v cc = max. v o = v cc ?? 1a i ozl (3-state output pins) v o = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) 50 90 200 m a v oh output high voltage v cc = min. i oh = ?0.1ma v cc ?0.2 ? ? v in = v ih or v il i oh = ?8ma 2.4 (5) 3?v v ol output low voltage v cc = min. i ol = 0.1ma ? ? 0.2 v in = v ih or v il i ol = 16ma ? 0.2 0.4 v i ol = 24ma ? 0.3 0.5 i off input power off leakage v cc = 0v, v in = 4.5v ? ? 1a i os short circuit current (4) v cc = max., v o = gnd (3) ?60 ?135 ?240 ma v h input hysteresis ? ? 150 ? mv i ccl quiescent power supply current v cc = max. ? 0.1 10 a i cch v in = gnd or v cc i ccz notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 3.3v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = vcc - 0.6v at rated current.
4 commercial and industrial temperature range idt49fct3805/a 3.3v cmos buffer/clock driver notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. per ttl driven input (v in = v cc -0.6v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i c formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f o n o ) i cc = quiescent current (i ccl , i cch and i ccz ) ? i cc = power supply current for a ttl high input (v i n = v cc -0.6v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f o = output frequency n o = number of outputs at f o all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 10 30 a ttl inputs high v in = v cc ? 0.6v (3) i ccd dynamic power supply current (4) v cc = max. v in = v cc ? 0.035 0.06 ma/mhz outputs open v in = gnd oe a = oe b = gnd per output toggling 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 0.9 1.6 outputs open v in = gnd f o = 25mhz 50% duty cycle v in = v cc ? 0.6v ? 0.9 1.6 oe a = oe b = v cc v in = gnd mon. output toggling v cc = max. v in = v cc ?2033 (5) ma outputs open v in = gnd f o = 50mhz 50% duty cycle v in = v cc ? 0.6v ? 20 33 (5) oe a = oe b = gnd v in = gnd eleven outputs toggling
5 idt49fct3805/a 3.3v cmos buffer/clock driver commercial and industrial temperature range notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. t plh , t phl , t sk (t) are production tested. all other parameters guaranteed but not production tested. 4. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. switching characteristics over operating range - industrial (3,4) fct3805 fct3805a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 50pf 1.5 5.8 1.5 5.2 ns t phl in a to oan, in b to obn r l = 500 ? t r output rise time ? 2 ? 2 ns t f output fall time ? 2 ? 2 ns t sk(o) output skew: skew between outputs of all banks of ? 0.6 ? 0.6 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 1 ? 1 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1.5 ? 1.2 ns packages at same power supply voltage, temperature, package type and speed grade t pzl output enable time 1.5 6.5 1.5 6 ns t pzh oe a to oan, oe b to obn t plz output disable time 1.5 5.5 1.5 5 ns t phz oe a to oan, oe b to obn switching characteristics over operating range - commercial (3,4) fct3805 fct3805a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 50pf 1.5 5.8 1.5 5 ns t phl in a to oan, in b to obn r l = 500 ? t r output rise time ? 2 ? 2 ns t f output fall time ? 2 ? 2 ns t sk(o) output skew: skew between outputs of all banks of ? 0.5 ? 0.5 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 1 ? 1 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1.5 ? 1.2 ns packages at same power supply voltage, temperature, package type and speed grade t pzl output enable time 1.5 6.5 1.5 6 ns t pzh oe a to oan, oe b to obn t plz output disable time 1.5 5.5 1.5 5 ns t phz oe a to oan, oe b to obn
6 commercial and industrial temperature range idt49fct3805/a 3.3v cmos buffer/clock driver d.u.t. v in v out v cc r t pulse generator 50pf 500 ? 500 ? 6v gnd control input output normally low output normally high 3v 1.5v 0v 3.5v 0v switch closed switch open v ol v oh 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable 3v 0v v oh t plh t phl v ol 1.5v 1.5v t r t f 2.0v 0.8v input output t plh t phl 3v 0v v oh 1.5v 1.5v v ol t sk(p) = |t phl - t plh | input output t plh1 output 1 output 2 t sk(o) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol input t phl1 t phl2 t sk(o) t sk(o) = |t plh2 - t plh1 | or |t phl2 - t phl1 | input t plh1 package 1 output t sk(t) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol t phl1 t phl2 t sk(t) t sk(t) = |t plh2 - t plh1 | or |t phl2 - t phl1 | package 2 output package delay test circuits and waveforms pulse skew - t sk(p) test circuits for all outputs definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test switch disable low 6v enable low disable high gnd enable high switch position output skew - t sk(x) output skew - t sk(o) package skew - t sk(t) notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: f 1.0mhz; t f 2.5ns; t r 2.5ns
7 idt49fct3805/a 3.3v cmos buffer/clock driver commercial and industrial temperature range ordering information idt49fct device type x package 3805 3805a non-inverting 3.3v buffer/clock driver so sog py pyg q qg small outline ic soic - green shrink small outline ic ssop - green quarter-size small outline ic qsop - green blank i commercial (0c to +70c) industrial (-40c to +85c) xxxx x package corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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